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ZL10060 MOPLL with IF AGC Amplifier Data Sheet Features * Highly integrated mixer/oscillator PLL and IF AGC amplifier for multi band analog/digital terrestrial tuners and/or cable tuners Low phase noise PLL frequency synthesizer AGC output level detect with digital controlled TOP threshold >50 dB Desired/Undesired ratio without pre filtering Separate analog and digital IF outputs >41 dB IF AGC Control range Power down modes to support power reduction initiatives Four independent GPO 48 pin MLP Package October 2005 * * * * * * * * Ordering Information ZL10060LDG1 48 Pin QFN* Trays ZL10060LDF1 48 Pin QFN* Tape and Reel *Pb Free Matte Tin -20C to +85C Description The ZL10060 is a 3 band MOPLL with IF AGC amplifier. It down-converts the RF channel to a standard IF followed by filtering and IF AGC amplification for the digital channel. Each band consists of a low noise preamplifier/mixer and local oscillator with an external varactor tuned tank circuit. An IF level detector is included for control of the RF AGC. The Take Over Point and time constant are both programmable. The ZL10060 has high signal level handling performance providing excellent performance in the presence of high level unwanted signals. All chip control is via I2C bus. If higher performance is required, an alternative part, ZL10063 is available with image reject down conversion. Applications * * * * DVB-T receiver systems ISDB-T receiver systems DVB-C cable receiver systems Terrestrial analog receivers Band Pass Filter Analog IF SAW Digital IF SAW Analog Analog IF Demod LNA and Tracking Filters ZL10060 Digital IF RF Input Digital Demod IF AGC GPO PLL AGC Det I2C Control I2C Tuning RF AGC VCO Tank Circuits Loop Filter Figure 1 - Basic Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2005, Zarlink Semiconductor Inc. All Rights Reserved. ZL10060 Table of Contents Data Sheet Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 RF Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 SAW Driver Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3 AGC Detector and ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.4 IF AGC Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.5 VCO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.6 PLL Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.7 General Purpose Switching Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.8 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.0 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 Programmable Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 PLL Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 Control Register - Byte 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6 Control Register - Byte 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.7 Control Register - Byte 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.8 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.0 Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.0 PIn Circuit Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.0 Absolute Maximum Ratings - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.0 Operating Range - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.0 Electrical Characteristics- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2 Zarlink Semiconductor Inc. ZL10060 List of Figures Data Sheet Figure 1 - Basic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3 - Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4 - Low Band (VHF1) External Tank Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 5 - Mid Band (VHF3) External Tank Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 6 - High Band (UHF) External Tank Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 7 - Typical Application Circuit (DVB-T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 8 - Crystal Oscillator Circuit (4 MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 9 - Interstage Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 10 - Noise Figure Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3 Zarlink Semiconductor Inc. ZL10060 List of Tables Data Sheet Table 1 - Pin Names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2 - Programmable Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3 - Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 4 - Address Bit MA1 and MA0 Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 5 - Byte 1- LO Divider (MSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 6 - Byte 2 LO Divider (LSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 7 - Byte 4 PLL Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 8 - Charge Pump Current Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 9 - Reference Divide Ratio Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 10 - Byte 4 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 11 - Band Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 12 - Internal Circuit Block Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 13 - GPPO Output Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 14 - Byte 5 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 15 - AGC Decay Current Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 16 - AGC Threshold Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 17 - Byte 7 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 18 - ADC Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 19 - Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 20 - Read Data Format (MSB is transmitted first) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 21 - AGC Activity Flag Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 22 - ADC Output Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 23 - Optimum CP and LO Trim Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4 Zarlink Semiconductor Inc. ZL10060 Data Sheet IFAGC SAB SA ADC SDA SCL ADD AGCOP CNOPB CNOP CONT VccRF IFOPB IFOP VeeIF VccIF XTAL XCAP VccIF SDB SD VccDIG PUMP DRIVE 1 ZL10060 IFIPB IFIP VccOSC VeeOSC LHIPB LHOPB LHOP LHIP LMOPB LMOP LLOPB LLOP Vee (PACKAGE PADDLE) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Port Name IFAGC SAB SA ADC SDA SCL ADD AGCOP CNOPB CNOP CONT VccRF SIPB SIP GPP0 GPP1 IF amplifier AGC input SAW filter driver output SAW filter driver output External ADC input I2C bus serial data input/output I2C bus serial clock input I2C bus address selection input AGC output Analog converter output Analog converter output Paddle (Ground) SAW amplifier section supply SAW filter driver input SAW filter driver input General purpose switching port General purpose switching port Table 1 - Pin Names SIPB SIP GPP0 GPP1 GPP2 VeeRF LOIP IPREF MIDIP HIIP HIIPB GPP3 Figure 2 - Pin Diagram Function 5 Zarlink Semiconductor Inc. ZL10060 Pin No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Paddle Port Name GPP2 VeeRF LOIP IPREF MIDIP HIIP HIIPB GPP3 LLOP LLOPB LMOP LMOPB LHIP LHOP LHOPB LHIPB VeeOSC VccOSC IFIP IFIPB DRIVE PUMP VccDIG SD SDB VccIF XCAP XTAL VccIF VeeIF IFOP IFOPB Vee RF section ground Low band input Reference input for low and mid bands Mid band input High band inverse input High band input General purpose switching port Low band local oscillator output Low band local oscillator inverse output Mid band local oscillator output Mid band local oscillator inverse output High band local oscillator input High band local oscillator output High band local oscillator inverse output High band local oscillator inverse input Oscillator section ground Oscillator Vcc IF amplifier input IF amplifier inverse input Loop amplifier drive output Loop amplifier charge pump output Digital section supply SAW filter driver output SAW filter driver output IF amplifier section supply Reference oscillator feedback input Reference oscillator crystal drive IF amplifier section supply IF section ground IF amplifier output IF amplifier inverse output Global ground Table 1 - Pin Names (continued) Function General purpose switching port Data Sheet 6 Zarlink Semiconductor Inc. ZL10060 Data Sheet Figure 3 - Detailed Block Diagram 1.0 Functional Description The ZL10060 is a three-band RF mixer oscillator with on-board frequency synthesizer and IF AGC amplifier, integrating all tuner active circuitry after the tracking filter in a single package. It is intended for use in all band terrestrial tuners, and requires a minimum external component count. It contains all elements required for RF down conversion to a standard IF with the exception of external VCO tank circuits. In normal application the RF input is interfaced to the selected mixer oscillator preamplifier through the tuner prefilter and AGC stages. The ZL10060 provides an RF AGC control signal, which can be used to control the RF gain. The preamplifier output feeds the mixer stage where the required channel is down converted to the IF frequency. The local oscillator frequency for the down conversion is obtained from the on board PLL and local oscillator, with an external varactor tuned tank. The downconverted signal is then passed through an external filter into a SAW filter driver amplifier. This provides two output channels for hybrid analog and digital applications. 7 Zarlink Semiconductor Inc. ZL10060 An AGC IF amplifier is included which provides an output signal to a digital demodulator. The device is controlled through an I2C compatible interface. Data Sheet 1.1 RF Converter The ZL10060 contains three input stages to cover the VHF1, VHF3 and UHF frequency bands. The inputs would normally be driven by front end amplifiers and tracking filters. All three inputs are differential, however, the VHF1 and VHF3 inputs would normally be single ended. These inputs therefore can share a common input reference pin. The UHF input should be driven with a differential signal. The inputs are all high impedance. The differential converter IF output is then passed through an external interstage filter. This can be tuned for 36 MHz for DVB-T applications but can also be used at 44 MHz and 57 MHz to be compatible with other TV standards. The recommended filter circuit is shown in Figure 9. The design of this filter provides an impedance transformation as well as rejection of adjacent channels. A 0.5 dB Chebychev filter with 10 MHz bandwidth is recommended. This gives a flat response across the pass band and takes into account normal component tolerances. 1.2 SAW Driver Amplifier The output of the interstage filter then passes to the SAW filter drive amplifier. This provides further amplification and interfaces to the SAW filter. Two SAW filter drive outputs are provided for hybrid analog and digital applications. Both output stages are identical however the digital output (SD, SDB) should always be used for digital applications as the pin out of the device has been optimized to give the best isolation performance in this configuration. Output selection is programmable however it should be noted that the unselected output is not powered off but operates at a lower power level which means that a signal will still be present on the output. The differential outputs will drive a balanced SAW filter with a tuning inductor to resonate with the SAW filter input capacitance. The SAW filter can also be driven without the tuning inductor but with the addition of 350 ohm resistors to ground on the SAW driver outputs to increase the output drive capability. This will increase total current consumption by 14 mA. 1.3 AGC Detector and ADC The ZL10060 contains a broadband AGC detector circuit which provides an output to provide gain control for the RF frontend gain stages. The detector input signal is derived from the signal level in the SAW driver amplifier. The composite signal at this point is the wanted signal plus adjacent channels (N +/- 1, N +/- 2, N +/- 3). The AGC detector threshold point at which the agc output becomes active can be programmed to one of eight levels via the I2C interface. When the composite level reaches the agc threshold, the agc output pin will be active. The AGC attack current is fixed, however, the decay current can be programmed to two levels. The agc output can only drive a high impedance e.g., a dual gate FET. If RF gain control uses a PiN diode then a simple buffer circuit will be required. An AGC flag output is also available through the I2C interface. This indicates when the AGC output is active i.e., less than 4 volts. The agc output level can also be monitored by an on chip 3 bit ADC. Although the ADC is 3 bits, only 5 levels are available. Alternatively the ADC can be programmed to measure the voltage on an external pin (ADC Pin 4). 1.4 IF AGC Amplifier The AGC amplifier amplifies the output of the SAW filter for the digital channel and provides a differential output to the demodulator. The analog gain control signal is normally derived from the demodulator. At least 41 dB of gain control is provided. The AGC amplifier can be powered down independently of the rest of the device if not required. This mode could be used in analog applications to reduce overall power consumption. 8 Zarlink Semiconductor Inc. ZL10060 1.5 VCO Data Sheet Separate VCO's are provided for each band. The oscillator circuits are on chip however the tank circuitry is external. All three oscillators are differential. The typical external tank circuits are shown in Figures 4, 5 and 6. It is essential to take care to minimize track lengths and parasitics when designing the PCB layout to obtain best performance. The close-in phase noise of the local oscillator can be optimized at the programmed operating frequency by a programming bit which increases bias current in the VCO. . R_bias LLOPB Cs pF L1 nH Vvar LLOP R_bias Figure 4 - Low Band (VHF1) External Tank Circuit R_bias LMOPB Cs pF L1 nH Vvar LMOP R_bias Figure 5 - Mid Band (VHF3) External Tank Circuit 9 Zarlink Semiconductor Inc. ZL10060 Data Sheet LHIPB LHOPB LHOP LHIP Cp Cp Cp L1 nH R_bias Cs pF Cp R_damp R_bias Vvar Figure 6 - High Band (UHF) External Tank Circuit 1.6 PLL Frequency Synthesizer The PLL frequency synthesizer section contains all the elements necessary, with the exception of a frequency reference and loop filter to control a varicap tuned local oscillator, to form a complete PLL frequency synthesized source. The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with good phase noise performance. It can be operated with comparison frequencies appropriate for frequency offsets as required in digital terrestrial (DTT) receivers. The LO input signal from the selected oscillator section is routed to an internal preamplifier, which provides gain and reverse isolation from the divider signals. The output of the preamplifier interfaces directly to the 15-bit programmable divider, which is of MN+A architecture, with a 16/17 dual modulus prescaler. The A counter is 4-bits, and the M counter is 11 bits. The output of the programmable divider is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency which is derived either from the on-board crystal controlled oscillator, or from an external reference source. In both cases the reference frequency is divided down to the comparison frequency by the reference divider, which is programmable into 1 of 16 ratios. The output of the phase detector feeds a charge pump and loop amplifier section, which when used with an external loop filter, integrates the current pulses into the varactor control voltage. The programmable divider output, Fpd, divided by two and the reference divider output, Fcomp, can be switched to port P0 by programming the device into a test mode. The PLL includes a lock detect circuit. The lock detect output is available by reading the Status byte on the I2C interface 1.7 General Purpose Switching Ports The ZL10060 has four output switching ports. Three of these ports (GPP[3:1]) incorporate a 10 kohm pull up resistor. The remaining port (GPP0) is an open collector switch. These ports can be used for switching external RF input stages for example. Ports GPP[1:0] can also be used as test outputs for debug purposes. 1.8 I2C Interface The ZL10060 is controlled by an I2C data bus and is compatible with both 3.3 V and 5 V control levels. Data and Clock are fed in on the SDA and SCL lines respectively as defined by I2C bus format. The device can either accept data (write mode), or send data (read mode). The LSB of the address byte (R/W) sets the device into write mode if it is low, and read mode if it is high. The device can be programmed to respond to 1 of 4 addresses, 10 Zarlink Semiconductor Inc. ZL10060 Data Sheet which enables the use of more than one device in an I2C bus system. The address is selected by applying a voltage to the `ADD' input. When the device receives a valid address byte, it pulls the SDA line low during the acknowledge period, and during following acknowledge periods after further data bytes are received. When the device is programmed into read mode, the controller accepting the data must pull the SDA line low during all status byte acknowledge periods to read another status byte. If the controller fails to pull the SDA line low during this period, the device generates an internal STOP condition, which inhibits further reading. 2.0 Programming The ZL10060 is fully programmable through the I2C interface. The device can also output data to the controller. 2.1 Programmable Features Feature Description RF programmable divider Reference programmable divider Band selection AGC Threshold AGC Decay Charge pump current IF amplifier function SAWF output select Ports GPP[3:1] Programs main PLL main divider Programs PLL reference divider to set required frequency step Selects RF input and appropriate LO oscillator. Sets the Input Power Level Threshold at which the AGC detector starts to generate a control level. Sets the AGC decay current. Selects one of the four charge pump current settings. The IF amplifier can be enabled independently of other circuit blocks. Select the analog or digital SAW driver output. These are configured as NPN buffers with 10 kohm pull-up resistors to Vcc. Logic `1' = on Logic `0' = off; default on power up This is configured as a NPN open collector buffer. Logic `1' = on Logic `0' = off; default on power up Adjusts the VCO bias current to provide optimum phase noise performance. Select either the internal AGC detect output level or the external level applied to the ADC input pin. The ZL10060 has various power saving modes. Test modes to monitor and control internal PLL signals. Table 2 - Programmable Features PORT GPP0 VCO Trim ADC input Select Programmable power Test modes 2.2 Register Map There are a total of 7 write registers, the first of which is the Address register. The control registers are described in detail in the following section. The MSB of each register is written first. After reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines whether the byte is interpreted as a byte 2 or 4, a logic '0' indicating byte 2, and a logic '1' indicating byte 4. Having 11 Zarlink Semiconductor Inc. ZL10060 Data Sheet interpreted this byte as either byte 2 or 4 the following data byte will be interpreted as byte 3 or 5 respectively. Byte 5 will be followed by byte 6 or a stop condition. Byte 6 will be followed by byte 7 or a stop condition. Byte 7 will be followed by a stop condition or a byte 2 or byte 4 as described above. Further data bytes can be programmed following the above-described protocol. A STOP condition can be generated after any data byte, if however it occurs during a byte transmission, the previous byte data is retained. To facilitate smooth fine tuning, the frequency data bytes are only accepted by the device after all 15 bits of frequency data have been received, or after the generation of a STOP condition. MSB LSB ACK 7 Address Programmable divider Programmable divider Control data Control data Control Data Control Data 6 1 D14 D6 C1 BS0 LO0 X 5 0 D13 D5 C0 SL1 ATC AGD 4 0 D12 D4 R4 SL0 IFE ADS 3 0 D11 D3 R3 P3 X T3 2 MA1 D10 D2 R2 P2 AT2 T2 1 MA0 D9 D1 R1 P1 AT1 T1 0 0 D8 D0 R0 P0 AT0 T0 A A A A A A A Byte 1 Byte 2W Byte 3W Byte 4W Byte 5W Byte 6W Byte 7W 1 0 D7 1 BS1 LO1 SAS Table 3 - Control Registers A MA1, MA0 D14-D0 R4-R0 C1, C0 BS1-BS0 SL1-SL0 SAS P3-P0 ADS ATC AGD AT2:AT0 LO1:LO0 T3-T0 IFE Acknowledge bit Address bits Programmable division ratio control bits Reference division ratio select Charge pump current select Band select bits Power down modes SAWF drive output select P3-P0 port output states ADC input select AGC Decay Current AGC Disable AGC Onset threshold Control LO trim control bits Test mode control bits IF AGC amplifier enable 12 Zarlink Semiconductor Inc. ZL10060 Data Sheet Details of the programming registers are shown in the following sections. Default values on power up are also shown. 2.3 Address Register The ZL10060 address (MA1, MA0) are determined by the voltage set at the address pin (ADD) as shown in Table 4. Address Select (Byte 1) MA1 MA0 Address Input Voltage Level 0 0 1 1 0 1 0 1 0 - 0.1Vcc (Connect to Vee) 0.2Vcc - 0.3Vcc (Open circuit) 0.4 Vcc - 0.6 Vcc (30K to Vcc) 0.9 Vcc - 1.0 Vcc (Connect to Vcc) Table 4 - Address Bit MA1 and MA0 Settings 2.4 PLL Registers Bytes 2,3 and 4 are used to program the PLL. Bit Field Name Default Description 7 6:0 D[14:8] 0 0 Not used MSB bits of LO Divider register. Table 5 - Byte 1- LO Divider (MSB) Bit Field Name Default Description 7:0 D[7:0] 0 LSB bits of LO Divider register. Table 6 - Byte 2 LO Divider (LSB) The LO frequency will not be updated until both Byte 1 and Byte 2 have been programmed. Bit Field Name Default Description 7 6:5 4:0 C[1:0] R[4:0] 1 0 10011 Not Used Charge pump current. Reference divider control. Table 7 - Byte 4 PLL Control The charge pump current values are selected from the following table: C1 C0 Current A 0 0 +-155 Table 8 - Charge Pump Current Selection 13 Zarlink Semiconductor Inc. ZL10060 C1 C0 Current A Data Sheet 0 1 1 1 0 1 +-330 +-690 +-1450 Default State on power up = 00 Table 8 - Charge Pump Current Selection The reference divider ratio can be selected from the following table: R4 R3 R2 R1 R0 Ratio 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 16 32 64 128 20 40 80 160 24 48 96 192 28 56 112 224 Default State on power up = 10011 Table 9 - Reference Divide Ratio Settings 14 Zarlink Semiconductor Inc. ZL10060 2.5 Control Register - Byte 5 Bit Field Name Default Description Data Sheet 7:6 5:4 3:0 BS[1:0] SL[1:0] P[3:0] 11 01 0 Band Switching Power-up modes General Purpose Output ports Table 10 - Byte 4 Control The band switching is controlled as shown below: BS1 BS0 Band Selected 0 0 1 1 0 1 0 1 LO Band MID Band HI band All off Default state on power up = 11 Table 11 - Band Selection The various power-up modes are shown below. The IF AGC amplifier is controlled separately The I2C interface and crystal oscillator circuit is active in all modes. Power Mode SL1 SL0 I2C interface and registers Crystal oscillator Section Status PLL & VCO Converter and IF stages 0 1 1 X 0 1 Sleep PLL and VCO enabled Full Enabled Enabled Enabled Enabled Enabled Enabled Disabled Enabled Enabled Disabled Disabled Enabled Table 12 - Internal Circuit Block Control The ZL10060 has four output ports. Ports [3:1] have an internal 10 kohm pull up resistor to Vcc. P0 is open collector. Function Bit 0 1 GPP0 output Enable GPP1 output Enable GPP2 output Enable GPP3 output Enable P0 P1 P2 P3 Off (High Impedance) Off Off Off On (Current Sink) On (Current Sink) On (Current Sink) On (Current Sink) Table 13 - GPPO Output Port Control 15 Zarlink Semiconductor Inc. ZL10060 2.6 Control Register - Byte 6 Bit Field Name Default Description Data Sheet 7 6 5 4 3 2:0 LO1 LO0 ATC IFE AT[2:0] 0 0 0 0 0 0 VCO Bias Trim Not used AGC Decay current select IF AGC Amplifier enable (1 = On) Not used AGC Threshold Select Table 14 - Byte 5 Control The VCO bias trim adjusts the VCO bias to give optimum close-in phase noise. In general this should be set to 1 for the lower third of the VCO frequency range. The AGC attack current is fixed at 100 A however the agc decay current can be programmed to one of two values as shown below. ATC AGC Decay Current (A) 0 1 10.0 0.3 Table 15 - AGC Decay Current Setting 16 Zarlink Semiconductor Inc. ZL10060 Data Sheet The AGC threshold can be programmed using the AT[2:0] bits. Note that the programmed value is dBV peak. AT2 AT1 AT0 AGC Threshold (peak signal in dBV into detector) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 120 118 116 114 112 110 107 104 Default state on power up = 000 Table 16 - AGC Threshold Selection 2.7 Control Register - Byte 7 Name Default Description Bit Field 7 6 5 4 3:0 SAS AGD ADS T[3:0] 1 0 1 0 0 Digital SAW Drive Output Select (1 = Digital) Not used AGC Detector Enable (0 = Enabled) ADC Input select Test Bits Table 17 - Byte 7 Control The ADC input selection is shown in the table below ADS ADC Function 0 1 AGC Output External ADC input Table 18 - ADC Input Selection The test bits T[3:0] allow internal PLL signals to be monitored and also to manually control charge pump current and AGC detector output. This facilities may be useful during debug. The test bit selection is shown below. The reserved test modes should not be used. T3 T2 T1 T0 Test Mode Description 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 Normal operation Reserved Test Mode AGC Sink, Force Iagc = -100 A AGC Source, Force Iagc = 10 A P0 = Output of AGC bias DAC Table 19 - Test Modes 17 Zarlink Semiconductor Inc. ZL10060 T3 T2 T1 T0 Test Mode Description Data Sheet 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 Reserved Test Mode Reserved Test Mode Reserved Test Mode Reserved Test Mode Reserved Test Mode Charge pump sink * Status byte FL set to logic `0' Charge pump source * Status byte FL set to logic `0' Charge pump disabled * Status byte FL set to logic `1' Port P0 = Fpd/2 Charge pump sink * Status byte FL set to logic `0' Port P0 = Fcomp Charge pump source * Status byte FL set to logic `0' Port P0 = Fcomp Charge pump disabled * Status byte FL set to logic `1' Port P0 = Fcomp 1 1 1 0 1 1 1 1 Table 19 - Test Modes (continued) 2.8 Read Mode When the device is in read mode, the status byte read from the device takes the form shown in Table 20. MSB LSB ACK 7 Address Status Byte 6 1 FL 5 0 1 4 0 1 3 0 AGF 2 MA1 V2 1 MA0 V1 0 0 V0 A A Byte 1 Byte 2R 1 POR Table 20 - Read Data Format (MSB is transmitted first) The following describes data read through the read byte; * Bit 7 (POR) is the power-on reset indicator, and this is set to a logic '1' if the Vcc supply to the device has dropped below 3 V (at 25C), e.g., when the device is initially turned ON. The POR is reset to '0' when the read sequence is terminated by a STOP command. When POR is set high this indicates that the programmed information may have been corrupted and the device reset to power up condition. Bit 6 (FL) is the PLL lock flag and indicates whether the device is phase locked, a logic '1' is present if the device is locked, and a logic '0' if the device is unlocked. The FL bit is set after 64 consecutive comparison cycles in lock. * 18 Zarlink Semiconductor Inc. ZL10060 * Bit 3 (AGF) is the AGC detector flag and indicates whether the AGC detector is active. AGF AGC Activity Flag Data Sheet 0 1 AGC active, VAGC < 4 V External RF LNA gain is reduced AGC not active, VAGC >4 V External RF LNA gain is at maximum Table 21 - AGC Activity Flag Settings * Bits 2:0 (V2:V0) contain the ADC output data. The ADC output is sampled on the ACK clock of the read address byte. Input Level (V) V2 V1 V0 < 0.32 Vcc 0.32Vcc to 0.48Vcc 0.48Vcc to 0.64Vcc 0.64Vcc to 0.80Vcc > 0.80Vcc 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 Table 22 - ADC Output Values 19 Zarlink Semiconductor Inc. 3.0 PLL loop filter C21 8.2nF TP3 R9 1k 1k +30V TP R5 D3 1k 1k BB555 R3 D2 BB640 R1 D1 BB640 C20 C17a 10nF 220pF 20k gnd R8 100nF C46 gnd R6 3k3 R4 3k3 R2 3k3 R7 27pF 68pF 100pF 10k +5V C16 C30 L6 gnd gnd gnd C10 L4 Coil Data 100nH (air) C2 L2 L2: 100nH as 8.5 turns 24 swg (0.56mm) En Cu on 2.5mm dia close wound L4: 12.5nH as 30mm 24 swg En Cu formed into 2.5 turns on 2mm dia space wound L6: 2n5H as 16mm 24 swg En Cu formed into 5/4 turns on 2mm dia space wound C54 100pF 0R TR1 gnd gnd R13 C32 100pF 6R8 6R8 10nF 2n5H (air) 12n5H (air) SF1 C26 1nF 18k R16 gnd 34 33 32 29 35 28 27 36 31 30 26 25 BCW33 R14 C13 C12 C14 gnd 2p2F 2p2F 2p2F 2p2F R15 C11 2 5 1nF X6874D IN+ OP+ 4 Applications Information INIFIN LHIP IFINB LLOP GND 1 C27 OP- 3 LHIPB LHOP LMOP LLOPB LHOPB VccOSC 37 DRIVE PUM P VccDIG SD 1nF VeeOSC +5V GPP3 HIIPB HIIP M IDIP RFINB LOIP VeeRF GPP2 GPP1 GPP0 SIP SIPB VccRF Gnd 13 14 15 16 17 GPP2 GPP1 gnd gnd GPP0 +5V 18 gnd 19 20 gnd 21 C8 22 23 1 24 2 LMOPB gnd GPP3 3 4 C33 10nF C37 gnd 39 40 38 C40 100pF 100pF RF IN (UH F) 6 gnd 10nF C3 C5 1nF L13 nm nm R26 R27 SDB VccIFO XCAP XTAL 1.5uH C15 X4 1nF nm X6 X2 nm 0R 10nF RF IN (VH 3) F gnd C1 C19 47pF gnd 41 +5V 42 IC1 C7 A typical applications circuit is shown in the following diagram. ZL10060 20 C18 43 44 150pF 10nF ZL10060 ZL1006X gnd gnd gnd X1 4.000MHz X7 X3 nm +5V X5 nm 0R C28 27pF C35 10nF 45 VccIF VeeIF IFOP IFOPB 46 RF IN (VH 1) F gnd IFAGC SAB SA ADC SDA SCL ADD AGCout CNOPB CNOP C22 10nF Conti nuity 1 2 3 4 5 6 7 8 9 10 11 12 0 Figure 7 - Typical Application Circuit (DVB-T) C23 10nF Zarlink Semiconductor Inc. gnd 47 48 IF Output to Digital Demodulator Interstage Filter L9 680nF C24 1nF L11 680nF C39 gnd C25 L10 C49 10nF C4 18pF gnd +30V +5V IFAGC +5V C38 12pF 12pF 680nH 12pF C53 C48 12pF 10nF C56 1 2 3 4 + + C36 IFAGC ADC gnd 10uF 2u2F gnd C47 gnd 100pF C6 18pF C34 10nF AGC Out Analog SAW 10nF C51 Driver Output C50 10nF gnd SCL SDA I2C Data Sheet ZL10060 Data Sheet The low (VHF1) and Mid (VHF3) bands are single ended however the high band (UHF) should be differential. All IF signals are differential. It is essential to have good RF layout around the RF stages, i.e., RF inputs and the VCOs. Track lengths around the VCO's should be minimized to reduce track inductance. The layout should be organized to give good isolation between the IF signal paths. In particular good isolation is required between the outputs and inputs of the IF AGC amplifier. Isolation across the SAW filter is also important to ensure rejection of unwanted adjacent signals. This can be achieved by routing input and output tracks on opposite sides of the board. It is also important to have good isolation between the high level IF signal and the crystal oscillator circuit to minimize any interactions. Care should be taken when locating IF tuning inductors to ensure there is no radiation to other parts of the circuit. The crystal oscillator can also provide a clock signal to the demodulator. This can be done by taking the oscillator signal from the crystal series capacitor (27 pF) as shown in the following diagram. Figure 8 - Crystal Oscillator Circuit (4 MHz) 21 Zarlink Semiconductor Inc. ZL10060 Data Sheet The interstage filter between the converter outputs provides some rejection of adjacent channels (N +/- 2).The recommended values are shown in Figure 9. The choice of components is important not only to give a flat response but also to provide an impedance transformation. The specified noise figure for the low and mid bands assumes that there will be a network before the device to provide image rejection. In a tuner this would be part of the input tracking filters but for test purposes a network is shown in Figure 10. Vcc R source R source SAWF Drive Amplifier Input L1 CNOPB L1 SAMPIPB L2 C1 C2 Rterm SAMPIP Rterm Cc C1 C1 Cc CNOP Type IF MHz 0.5 dB BW MHz Rsource Rterm Component values L1 L2 C1 Cc C2 0.5 dB Chebycheff 36 12 700 350 560 560 18 12 8.2 Figure 9 - Interstage Filter 22 Zarlink Semiconductor Inc. ZL10060 Data Sheet 50 C1 1nF MIDIP/LOIP Vs L1 C2 1nF IPREF DUT Gnd Frequency Band LO RF IN C1 L1 C2 LOW LOW MID MID 90 200 240 500 MHz 46 156 196 446 MHz 20 8 8 2.1 pF 299 65 41 21 nH 20 8 8 4 pF Figure 10 - Noise Figure Measurement Conditions The optimum charge pump and LO trim settings for the application circuit shown in Figure 8 are shown in the table below. These give the optimum phase noise performance for the circuit shown. The changes in charge pump current compensate for frequency and VCO gain variations. Charge Pump Setting CP LO Trim LO1 Frequency Range VHF1 50 -110 MHz VHF1 100 -160 MHz VHF3 160 - 250 MHz VHF3 250 - 350 MHz VHF3 350 - 450 MHz UHF 450 - 500 MHz UHF 500 - 700 MHz UHF 700 - 800 MHz UHF 800 - 850 MHz 01 10 10 01 10 00 01 10 11 1 1 1 0 0 1 1 1 1 Table 23 - Optimum CP and LO Trim Settings 23 Zarlink Semiconductor Inc. ZL10060 4.0 Pin No. Data Sheet PIn Circuit Information Pin Name Port Sense Function Schematic IFA G C 3K V REF 1 IFAGC Input IF AGC control 3K 2, 3 SAB, SA Output, Output SAW filter driver output A inverse SAW filter driver output A V cc SA 50 SAB 4 ADC Input ADC input V cc ADC 5 SDA Bi-directional I2C bus serial data input/output V cc SDA 6 SCL Input I2C bus serial clock input V cc SCL 24 Zarlink Semiconductor Inc. ZL10060 Pin No. Pin Name Port Sense Function Schematic Data Sheet 7 ADD Input I2C address select V cc 63k ADD 3k 21k 8 AGCOP Output AGC output V cc 100 AGCOP 1K 9, 10 CNOPB, Output, CNOP Output Converter Output inverse Converter Output 500 CNOP Vcc 500 CNOPB 11 12 13, 14 Cont VccRF SIPB SIP Supply Input, Input Paddle RF section supply SAW filter driver input inverse, SAW filter driver input V cc S IP S IP B 250 1 .1 K 15 GPP0 Output Switching port/Test output 1 GPP0 25 Zarlink Semiconductor Inc. ZL10060 Pin No. Pin Name Port Sense Function Schematic V cc 10K Data Sheet 16 GPP1 Output Switching port/Test output 2 GPP1 GPP2 GPP3 17 18 19, 20, 21 GPP2 VeeRF LOIP IPREF MIDIP Output Supply Input, Input, Input Switching port RF section ground Low band input, Mid- and Low-band i/p reference, Mid-band input As GPP1 (pin16) - LO IP M ID IP IP R E F 22, 23 HIIP, HIIPB Input, Input Hi-band input, Hi-band input inverse H IIP H IIP B 24 25, 26 GPP3 LLOP, LLOPB Output Output Switching Port Low band oscillator output, Low-band oscillator output inverse As GPP1 (pin16) LLOP LLOPB 27, 28 LMOP, Output, LMOPB Output Mid-band oscillator output, Mid-band oscillator output inverse LMOP LMOPB 26 Zarlink Semiconductor Inc. ZL10060 Pin No. Pin Name Port Sense Function Schematic Vcc 350 LHOPB LHIP 350 Data Sheet 29, 30, 31, 32 LHIP, LHOP, LHOPB, LHIPB Input, Output, Output, Input High band oscillator input, High-band oscillator output, High-band oscillator output inverse, High-band oscillator input inverse LHOP LHIPB 33 34 35, 36 VeeOSC Supply VccOSC Supply IFIP, IFIPB Input, Input LO ground LO supply IF AGC amp input, IF AGC amp input inverse - IF IP IF IP B 37, 38 DRIVE, PUMP Output, Output Loop amplifier drive output, Loop amp charge pump output Vcc PUMP DRIVE 340 39 40, 41 VccDIG Supply SD, SDB Output, Output Digital section supply SAW filter driver output D, SAW filter driver o/p D inverse V cc SD 50 SDB 42 43 VccIFO XCAP Supply Input SAWF output supply Reference osc feedback input V cc 110 XTAL XCAP 0 .2 m A 44 XTAL Output Reference osc crystal drive See XCAP (pin 43) 27 Zarlink Semiconductor Inc. ZL10060 Pin No. Pin Name Port Sense Function Schematic Data Sheet 45 46 47, 48 VccIF VeeIF IFOP, IFOPB Supply Supply Output, Output IF AGC supply IF AGC ground IF AGC amp output, SAW filter driver o/p D inverse Vcc IF O P Paddle Vee - - - 28 Zarlink Semiconductor Inc. ZL10060 5.0 Absolute Maximum Ratings - All voltages are referred to Vee at 0 V. Characteristic Min. Max. Units Conditions Data Sheet Supply voltage RF input voltage Maximum voltage on SDA, SCL Max voltage on all remaining signal pins Total port current Storage temperature Junction temperature Package thermal resistance (chip to ambient) ESD protection -0.3 6 117 5.5 V dBV Transient condition only V V mA oC oC o Vcc = 0 to 5.5V The voltage on any pin must not exceed 6 V -0.3 -55 Vcc+0.3 20 150 125 27 Power applied Package paddle soldered to ground Mil-std 883B method 3015 cat1 C/W kV 1.25 6.0 Operating Range Characteristic All voltages are referred to Vee at 0 V. Min. Max. Units. Conditions Supply voltage Supply voltage Ambient Temperature Low Band Frequency Mid Band Frequency High Band Frequency 4.5 4.75 -20 50 200 400 5.5 5.25 85 300 500 950 V V oC Functional operation, specification not guaranteed Full specification MHz MHz MHz 29 Zarlink Semiconductor Inc. ZL10060 7.0 Data Sheet Electrical Characteristics- Test conditions (unless otherwise stated). T = 25oC, Vee= 0 V, Vcc = 5 V, IF Frequency = 36 MHz. All signals are differential with the exception of VHF1 and VHF3 inputs. Characteristic Supply current Min. Typ. Max. Units Conditions Normal operation All sections active All sections active except AGC IF amplifier Sleep Mode 117 110 92 85 9 33 140 134 mA mA mA mA mA mA Total Current - UHF band All switching ports off Total Current - VHF Bands All switching ports off UHF Band. Switching ports off VHF Bands. Switching ports off Crystal oscillator and data interface enabled PLL and crystal oscillator enabled Composite system to SAW Filter driver outputs VHF1 Band Conversion gain Conversion gain Noise Figure OPIP3 Output level causing 1% cross modulation Output level causing 1.5 kHz FM I2C bus transmission induced LO frequency modulation 29 29 32 32 9 35 35 11 dB dB dB dBV dBV dBV kHz RFin = 54 MHz. Single ended input RFin = 155 MHz. Single ended input Rs = 50 , SSB with input matching network. See Figure 10. Two output tones at 110 dBV Note 2 Note 3 Transmission repetition rate of 20 msec minimum with no change to previously loaded data, at 100 kHz SCL rate Local oscillator sidebands induced by an input carrier at 80 dBV offset from local oscillator by 100 kHz Residual FM induced on local oscillator by 20 mVp-p ripple on Vcc at 500 kHz 135 113 113 146 120 120 2.5 N+5 Direct modulation of VCO Supply ripple spurious -40 dBc -40 dBc Local oscillator leakage to any band input IPIP2 134 30 143 dBV dBV Two input tones at 87 dBV at 90 MHz and 66 MHz with local oscillator at 114 MHz 30 Zarlink Semiconductor Inc. ZL10060 Characteristic Min. Typ. Max. Units Conditions Data Sheet IPIP3 112 120 dBV Desired = 54 MHz at 45 dBV Undesired = 60 and 72 MHz at 87 dBV Desired = 155 MHz at 45 dBV Undesired = 161 and 173 MHz at 87 dBV IPIP3 112 119 dBV P1dB Output Impedance 93 106 100 10 dBV nH PLL Loop Bandwidth ~ 3 kHz fcomp = 166.7 kHz Phase Noise, SSB 1 kHz 10 kHz 100 kHz 10 MHz Reference spurs Phase Noise, SSB 10 kHz 100 kHz -97 -115 dBc/Hz dBc/Hz -90 -90 -95 -115 -70 -86 -106 -135 -50 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc Noise Floor Narrow PLL Loop Bandwidth fcomp = 62.5 kHz Composite system to SAW Filter driver outputs VHF3 Band Conversion gain Conversion gain Noise Figure OPIP3 Output level causing 1% cross modulation Output level causing 1.5 kHz FM I2C bus transmission induced LO frequency modulation 29 29 32 32 9 35 35 11 dB dB dB dBV dBV dBV kHz RFin = 164 MHz Single ended input RFin = 442 MHz Single ended input Rs = 50 , SSB with input matching network. See Figure 10. Two output tones at 110 dBV Note 2 Note 3 Transmission repetition rate of 20 msec minimum with no change to previously loaded data, at 100 kHz SCL rate 135 113 113 146 120 120 2.5 31 Zarlink Semiconductor Inc. ZL10060 Characteristic Min. Typ. Max. Units Conditions Data Sheet N+5 Direct modulation of VCO Supply ripple spurious - -40 dBc Local oscillator sidebands induced by an input 750 MHz carrier at 80 dBV offset from local oscillator by 100 kHz. Residual FM induced on local oscillator by 20 mVp-p ripple on Vcc at 500 kHz -40 dBc Local oscillator leakage to any band input IPIP2 134 30 143 dBV dBV Two input tones at 89 dBV at 198 MHz and 398 MHz with local oscillator at 240 MHz Desired = 165 MHz at 45 dBV Undesired = 171 and 183 MHz at 89 dBV Desired = 438 MHz at 45 dBV Undesired = 444 and 456 MHz at 89 dBV IPIP3 112 122 dBV IPIP3 112 119 dBV P1dB Output Impedance -95 107 100 10 dBV nH PLL Loop Bandwidth ~ 3 kHz fcomp = 166.7 kHz Phase Noise, SSB 1 kHz 10 kHz 100 kHz 10 MHz Reference spurs Phase Noise, SSB 10 kHz 100 kHz -94 -114 dBc/Hz dBc/Hz -90 -87 -92 -114 -70 -86 -106 -135 -50 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc Noise Floor Narrow PLL Loop Bandwidth fcomp = 62.5 kHz Composite system to SAW Filter driver outputs UHF Band Conversion gain Conversion gain Noise Figure OPIP3 35 35 38 38 6 41 41 8 dB dB dB dBV RFin = 450 MHz RFin = 866 MHz Rs = 50 , No image correction Two output tones at 110 dBV 135 146 32 Zarlink Semiconductor Inc. ZL10060 Characteristic Min. Typ. Max. Units Conditions Data Sheet Output level causing 1% cross modulation Output level causing 1.5 kHz FM I2C bus transmission induced LO frequency modulation 113 113 120 120 2.5 dBV dBV kHz Note 2 Note 3 Transmission repetition rate of 20 msec minimum with no change to previously loaded data, at 100 kHz SCL rate Local oscillator sidebands induced by an input 750 MHz carrier at 80 dBV offset from local oscillator by 100 kHz Residual FM induced on local oscillator by 20 mVp-p ripple on Vcc at 500 kHz N+5 Direct modulation of VCO Supply ripple spurious -30 dBc -40 dBc Local oscillator leakage to any band input IPIP2 125 60 159 dBV dBV Two input tones at 89 dBV at 198 MHz and 398 MHz with local oscillator at 240 MHz Desired = 438 MHz at 45 dBV Undesired = 444 and 456 MHz at 85 dBV Desired = 858 MHz at 45 dBV Undesired = 864 and 876 MHz at 85 dBV IPIP3 108 115 dBV IPIP3 108 112 dBV P1dB Output Impedance 91 99 100 10 dBV nH PLL Loop Bandwidth ~ 3 kHz fcomp = 166.7 kHz Phase Noise, SSB 1 kHz 10 kHz 100 kHz 10 MHz Reference spurs Phase Noise, SSB 10 kHz 100 kHz -91 -113 dBc/Hz dBc/Hz -80 -78 -89 -113 -70 -84 -106 -135 -50 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc Noise Floor Narrow PLL Loop Bandwidth fcomp = 62.5 kHz 33 Zarlink Semiconductor Inc. ZL10060 Characteristic Min. Typ. Max. Units Conditions Data Sheet AGC Detector and ADC Operating frequency range AGC Threshold Level ADC leakage current 16 120 72 MHz dBV AT[2:0] = 0 VADC = 4.0 V VADC = 0.5V See Tables 11 and 13 Always active unless disabled by bit AGD, as described in Tables 11 and 13 AGC attack current, triggered by detected level exceeding AGC attack point 60 -60 nA nA AGC source current 6.8 0.25 10 0.33 13.3 0.43 A A AGC sink current -65 -100 -145 A AGC sink current 90% rise and fall time AGC input level response 1 1 sec dB Change in input level for AGC sink current to change from high impedance to 90% of maximum value, with AGC operative AGC inactive Minimum gain required Maximum gain required Maximum external voltage range which can be applied to AGCOP when disabled Over normal operating range See Table 22 See Table 22 AGF flag set to 1 AGF flag set to 0 AGCOP output impedance AGCOP output voltage range 20 0.5 4 M V V Vcc-0.4 V External AGC voltage 0.5 AGCOP leakage current ADC step size, LSB ADC step size accuracy AGCout_flag High threshold AGCout_flag Low threshold IF amplifier -50 0.16Vc c 50 nA V 0.01Vc c V V Vcc0.66 Vcc0.76 Supply Current 25 mA 34 Zarlink Semiconductor Inc. ZL10060 Characteristic Min. Typ. Max. Units Conditions Data Sheet Frequency range Input impedance 16 1.5 2 72 2.8 1.5 MHz k pF dB dB dB dB VIFAGC = 3.0 V VIFAGC = 2.2 V VIFAGC = 1.2 V VIFAGC = 0.5 V Rs=50 dB Gain (Voltage conversion gain, differential source to maximum load as defined below) Noise Figure AGC range AGC control slope AGC input current Gain variation within channel 61 48 21 8 66 57 25 17 6.3 70 65 29 22 8.5 41 25 48 31 38 50 0.25 dB/V A 1.2VAGC2.2 dB Channel bandwidth 8 MHz within operating frequency range, with maximum load as defined below Two output tones at 109 dBV within output channel Gain range = 21 dB to maximum OPIP3 130 141 dBV Output impedance Maximum load condition 120 4.7 15 k pF Differential load I2C BUS SDA SCL Input high voltage Input low voltage Input current High 2.55 0 5.5 1.4 10 10 V V A A A Vin=5.5 V, Vcc=5.25 V Vin=5.5 V, Vcc=0 V Vin= 0 V, Vcc=5.25 V Input Current Low Hysteresis SDA output voltage -10 0.4 0.4 0.6 V V V kHz See Table 4 1 mA Vin=VccD Isink=3 mA Isink=6 mA SCL clock rate ADD (address) select Input high current 100 35 Zarlink Semiconductor Inc. ZL10060 Characteristic Min. Typ. Max. Units Conditions Data Sheet Input low current PLL Synthesizer -0.5 mA Vin=Vee Charge pump output current Charge pump output leakage Charge pump drive output current Crystal frequency Recommended crystal series ESR External reference input frequency External reference drive level 0.5 4 25 4 0.2 0.5 Phase detector comparison frequency RF division ratio Switching ports GPP3-GPP0 Sink current Pull up resistor GPP3- GPP1 Leakage current Note 1: Note 2: Note 3: Note 4: See Table 8 VPUMP=2 V +-3 10 nA mA 16 70 150 20 2 MHz Note 4 VDRIVE=0.7 V Application as in Figure 13 with 4 MHz crystal 4 MHz parallel resonant crystal Sine wave coupled through 10 nF capacitor Sine wave coupled through 10nF capacitor Recommended level for optimum phase noise at 4 MHz MHz Vpp Vpp 31.25 240 250 32767 kHz 10 10 10 mA k A Vport = 0.4 Vport = Vcc, Port P0 only 0 dBm =107 dBV. All input levels are specified as voltage that would be present if input signal generator was terminated in 50 ohms Wanted signal (picture carrier) = 101 dBmV at output. Undesired signal (sound carrier) at 5.25 MHz offset modulated with 1 kHz 80% AM. Increase undesired signal to give 1% AM on wanted signal. Wanted signal at 101 dBmV. Unwanted signal at 5.25 MHz offset modulated with 1 kHz 50% AM. Increase undesired signal to give 1.5 kHz FM on wanted signal Current into PUMP pin with 20 A current from DRIVE pin 36 Zarlink Semiconductor Inc. D D1 A A1 D2 E1 E E2 L b e SEATING PLANE c Zarlink Semiconductor 2003 All rights reserved. Package Code Previous package codes ISSUE ACN DATE APPRD. 1 25-02-2004 For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request. Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE |
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